Synaptic Weight Coverage and Potential Output in Synaptic Pass-Transistors

Abstract

In this work, we present the study on a weight modulation of a synaptic transistor with a charge trapping layer, demonstrating the voltage-to-voltage transfer by employing a load resistor at the output and the pass-transistor operation concept. The synaptic weight as a transfer-efficiency is defined with the synaptic output in terms of the equivalent transistor resistance and load. Since the channel resistance of synaptic transistor can be modulated by the charge trapping, the synaptic plasticity is explained with a relative dominance of the transistor's resistance with the fixed load resistance. To show the weight modulation following the theoretical analysis, respective simulations for the depression and facilitation are conducted.