Process Optimization and Device Characterization of Nonvolatile Charge Trap Memory Transistors Using In–Ga–ZnO Thin Films as Both Charge Trap and Active Channel Layers

Abstract

Charge-trap memory thin-film transistors (CTM-TFTs) using In-Ga-ZnO (IGZO) thin films as active channel and charge trap layers (CTLs) were fabricated and characterized. Technical strategies to optimize the device design parameters were categorized into the following three parts. At first, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O2</sub> conditions during the sputtering deposition of IGZO CTL were varied to 1%, 2%, and 5% to modulate the electronic natures of the IGZO films. The device using the CTL deposited at P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O2</sub> of 1% obtained the largest memory window and exhibited the fastest program speed. Second, to investigate the thickness effects of double-layered tunneling oxide, the configuration was varied to 3/3 nm and 5/5 nm. From the viewpoints of process window, the 5/5 nm configuration was chosen for stable device characteristics. At last, the effects of CTL thickness, which affects the number of trap sites and carrier concentration of the film, was carefully investigated. A 30-nm-thick CTL showed most desirable behaviors, including superior memory operation and uniformity. The CTM-TFTs fabricated with optimum conditions exhibited the memory margin in programmed currents between ON-and OFF-states of 2.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> at 1-μs program voltage pulses with ±20 V. Furthermore, the ION/OFF of five-orders-of-magnitude was obtained even after the lapse retention time for 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s.