Switched Capacitor based Area Efficient Positive and Negative Voltage Multiplier

Abstract

This paper discuss about a voltage multiplier stage, which can be used to generate either positive voltage or negative voltage. Proposed circuit require triple well technology and NMOS transistors for its implementation. For the positive voltage case, voltage multiplication efficiency achieved is 99% and for negative voltage case, multiplication efficiency achieved is 98%. As single circuit can generate both positive and negative voltages so the proposed multiplier circuit can be used to generate high on-chip positive and negative voltages, thus avoiding the use of separate charge-pump for positive and negative voltages and saving huge on-chip area corresponding to flying capacitors. This circuit is implemented in 110nm-BCD technology using standard NMOS transistors.