Area Efficient NMOS Based Positive and Negative Voltage Multiplier

Abstract

This paper presents NMOS based voltage multiplier circuit that can be used to generate both high positive and negative voltages from single charge-pump circuit. Basic, voltage multiplier unit consists of two phase clock signals, charge transfer NMOS transistors and bootstrapped configuration to boost the gate drive of NMOS transistors. Due to use of only NMOS transistors, output resistance of circuit is lower than conventional PMOS based circuits thus able to drive high load current. Electrical conditions of all devices used in the circuit is managed in such a way that there is no electrical stress across any device used in design. Circuit is design and implemented in BCD-110nm technology using conventional (No DMOS) transistors.