Survey: Design and of a Reconfigurable Arbiter Using AMBA

Abstract

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP).Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source of the performance bottlenecks. The arbiter plays a very important role to manage the resource sharing on the SOC platform. This paper presents a reconfigurable arbiter with various combinations of arbitration algorithms. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 μm cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to market, thus how to verify IP functionality on bus protocol is challenge. Traditional simulation-based bus protocol monitor scan check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule based bus protocol checker, it contain ns 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors’ history data that helps designer debug efficiently Keywords: Arbiter, Reconfigurable, System-on-chip, Arbitration Algorithm, FPGA, AMBA