Abstract

Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to-market, thus how to verify IP functionality on bus protocol is a challenge. Traditional simulation-based bus protocol monitors can check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule-based bus protocol checker, it contains 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors' history data that helps designer debug efficiently.

Full Text
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