Abstract

Surface potentials of operating pentacene thin-film transistors (TFTs) with two different contact geometries (bottom or top) were mapped by Kelvin probe force microscopy (KFM). The surface potential distribution was used to isolate the potential drops at the source and drain contacts. These potential drops were converted to resistances by dividing by the appropriate drain current values. The bottom contact TFTs were contact limited at large gate voltages, while the top contact TFTs were not contact limited. In both geometries, the contact and the channel resistances decreased strongly with increasing (negative) gate bias but did not depend strongly on the drain bias. This study demonstrates the utility of KFM for visualizing charge transport bottlenecks in operating pentacene devices and for correlating electrical behavior with device structure by comparison of surface potential and topographic maps.

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