Support Vector Machine working on FPGA and the segmentation method of brain MR screening

Abstract

Field Programmable Gate Arrays (FPGA Field Programmable Gate Array) are devices containing programmable digital blocks and connections and have the capabilities to work in a fast and flexible way. Complex designs can be easily developed with these programmable digital Gates. FPGA’s are small in size and can work as mobile, independent from the computer,at higher speeds.Support vector machine which are important machine learning algorithms is developed to solve the classification problems. In the literature, Support Vector Machines are one of the important machine learning algorithms which are one of the tasks of data mining developed for the solution of the classification problem . Tumor analysis, face recognition, topics such as creating a robotic eye are some of the current, important and difficult problems which researchers are working on intensively in the field of image processing. In tumor analysis performed on the computer, problems of being slow in processing of graphics and pictures and being not mobile are overcome with the FPGA hardware image processing. In this study, it is aimed to find the presence of the tumor region and demonstrating the results of the required analysis by performing more realistic tumor analysis using support vector machines running on the FPGA Hardware. Thus the design of a useful hardware that can be used in the field of health will be carried out. Generally, these processes are done by computers because it is more easier. Therefore, because the number of work is very few which performs the process as described with embedded systems, this project carries originality value. In addition, VHDL (Very High Speed Integrated Circuit Hardware Description Language) , which is one the hardware description languages specific to FPGA will be used. For evaluation of segmentation results Uniformity Measure (UM) it is used. Keywords: Field Programmable Gate Array, FPGA, very high speed ıntegrated circuit hardware description language, vhdl, segmentation, support vector machine