VHDL architecture for IEC 61499 function blocks

Abstract

IEC 61499 runtime systems to-date have focussed on software implementations deployed to various micro-processors. This study proposes a novel and viable architecture allowing IEC 61499 models to be deployed as custom logic within a field programmable gate arrays (FPGAs). A complier/translator has been developed, by the authors, capable of translating IEC 61499 models to their very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) equivalent in accordance with this architecture. This architecture, and the associated compiler/translator, thus facilitates an exploration of the runtime behaviour of IEC 61499 elements in the context of FPGAs. This study also reports on a case study that was performed on a specific test scenario to determine the suitability and performance of the described architecture and associated compiler/translator. It was thus found that deploying IEC 61499 models to FPGAs allows capitalising on the parallel execution capabilities of the FPGA, resulting in the ability to handle simultaneous events and to execute algorithms in parallel. It was also found that simple modifications to the architecture result in a more traditional sequential behaviour. Furthermore, the architecture is capable of delivering highly deterministic hard real-time implementations of IEC 61499 models.