Supply Voltage Scaling for Low Power

Abstract

This chapter focuses on supply voltage scaling which is the most effective way to reduce power dissipation. First, the challenges involved in supply voltage scaling for low power are highlighted. Then, the difference between constant-field and constant-voltage scaling are explained in the context of feature size scaling. The short-channel effects arising out of feature size scaling are also discussed. Architecture-level approaches for low power, using parallelism and pipelining are explored. Multi-core processor architecture as an approach for low power is explained. Voltage scaling techniques using high-level transformations are presented. The multilevel voltage scaling (MVS) approach is introduced and various challenges in MVS are discussed. The implementation of dynamic voltage and frequency scaling (DVFS) approach is presented. Then, a close-loop approach known as the adaptive voltage scaling (AVS) is implemented which monitors the performance at execution time to estimate the required supply voltage and accordingly voltage scaling is performed. Finally, subthreshold circuits are introduced that operate with a supply voltage less than the threshold voltage of the metal–oxide–semiconductor (MOS) transistors, resulting in a significant reduction of power dissipation at the cost of longer delay.