Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics

Abstract

This paper analyses the impact of gate engineering on the performance of gate engineered FinFETs for system-on-chip applications with high-k dielectrics. Equivalent oxide thickness of gate oxide can be reduced by the usage of high-k dielectric materials and it was found that by replacing high-k dielectric materials as gate oxide the performance of the device can be improved. Gate engineering technique used here is dual material gate technology and the simulations were done using Sentaurus simulator. The parameters such as ON current, OFF current, ION/IOFF ratio, DIBL (Drain Induced Barrier Lowering), normalized transconductance, transconductance generation factor, output resistance, intrinsic gain, and intrinsic gate capacitances were analyzed. A proper trading of Fin width, Fin doping and gate work function improves the short channel effects. The suitability of nanoscale dual material FinFETs for circuit applications was examined by comparing the performance of an inverter for different high-k dielectrics and the circuit showed a significant improvement in gain with increased k values.