Substrate Coupling in Smart Power Integration

Abstract

This chapter proposes two technologies to implement the smart power integrated circuits (ICs). The first is planar integration using the deep trench isolation technique; the second is the new stacked three-dimensional (3D) integration using through-silicon vias (TSVs). The chapter defines the impact of substrate perturbations due to the HV digital signal on the performance of low-voltage metal oxide semiconductor (MOS) devices. In smart power ICs, there have been substantial improvements in performance and reliability, as well as reductions in cost, compared to the discrete approach. In recent years, 3D integration technology has emerged. This technology uses TSVs and re-distribution layers to interconnect multiple active circuit layers. It is evident that nearly half the TSV voltage is dropped across the TSV oxide and the other half across the depleted region in the substrate, and a few potential contours are observed in the active regions of the MOS devices.