Low Residual Stress in Si Substrate of Annular-Trench-Isolated TSV

Abstract

Driven by the need of reduced energy consumption in devices, 3D integration technology by through silicon via (TSV) attracts increasing interests. However, high thermal stress is induced by the large mismatch of the coefficient of thermal expansion (CTE) among the different materials in TSV. The thermal stress is a serious reliability concern for TSV in 3D integration system. In order to solve the stress issues in 3D packaging technology with TSV, we proposed a structure as annular-trench-isolated (ATI) TSV with an extra Si ring between Cu core and SiO2 layer. In this paper, we presented the fabrication process of ATI TSV with two separate etching processes for the parylene-HT trench and solder core while remaining a Si ring between parylene-HT layer and solder core. Note that the trench is narrow with thickness of 2 µm, and its aspect ratio (AR) is high as 7. We successfully deposited the insulator of parylene-HT material in the whole annular trench between Si substrate and Si ring. And the uniformity of deposited parylene-HT layer was observed clearly by 3D X-ray computed tomography method as CT scan. Considering the high aspect ratio of our TSV, difficulty was expected during the conventional process, such as barrier deposition and Cu electroplating. Therefore, solder injection was implemented for depositing the material into the vias of ATI TSV. In order to understand the stress level after fabrication process, the residual stress was investigated with validated simulation model. A lower residual stress in Si substrate was observed in ATI TSV than that of regular TSV due to less solder volume and the redistribution of stress by Si ring in ATI TSV. During thermal cycling, the stress level increased with temperature decreasing from 125°C to -40°C for both ATI and regular TSV. The residual stress measurement of ATI TSV will be performed in further work.