Sub-0.25 micron silicon via etching for 3D interconnects

Abstract

Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar integrated circuits (ICs). Etching high aspect ratio submicron vias for inter-wafer connection is one of the key processing metrics for the wafer-level 3D technology platform. The ability to optimize the effects of the process parameters during via etching is vital for the fabrication of emerging hyperintegration technologies. This paper outlines the establishment of reactive ion etching protocols for fabrication of high aspect ratio silicon vias with minimum bowing employing the Bosch process. High aspect ratio submicron via patterns were transferred into silicon substrates using a Unaxis Versalock deep reactive ion etch (DRIE) tool. Through careful optimization of Bosch etch process conditions, successful etching of high aspect ratio (13:1) 200 nm via features was achieved.