Deep Reactive Ion Etched Submicron Beam/Trench Characterization

Abstract

Abstract Sub-micron width high aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool equipped with a time multiplexed plasma etch/passivation cycle scheme. The oxide mask is patterned by nanoimprint lithography and minimizes lateral trench etching by adjusting the significant etch parameters. High aspect ratio trench arrays 350nm wide with a 700nm period are etched to a depth of 10 μm with typical sidewall asperities on the order of 30nm. A dual etch process is used to reduce scalloping near the trench surface using HBr/Cl to etch the initial 500nm followed by the STS process using C4F8/SF6 chemistry. The dual etch process resulted in a reduction of sidewall asperities from 75nm to less than 25nm. In addition, the dual etch process reduced the trench array depth variation from a measured standard deviation of 0.7 to 0.1 representing significant improvement of etch repeatability across the wafer sample.