Submicron high-aspect-ratio silicon beam etch

Abstract

High aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool. Process input parameters are varied using high/low values for etch cycle time, passivation cycle time, RF power, and SF<SUB>6</SUB> flow rate. The silicon etch process is characterized using photo-resist masked trench arrays varied from 1.5micrometers through 6micrometers in both width and spacing. A design of experiments (DOE) approach is used to model the following measured outputs: 1) trench depth (R<SUP>2</SUP>=0.985), 2) lateral trench etch (R<SUP>2</SUP>=0.852), 3) trench sidewall angle (R<SUP>2</SUP>=0.815), and 4) aspect ratio dependent etch (R<SUP>2</SUP>=0.942), where R<SUP>2</SUP> represents the correlation between actual and model predicted values. The presented characterization models are employed to form beams as small as 300nm wide beams etched to a depth &gt;15micrometers with near vertical sidewalls using standard photolithography equipment. In addition, the provided models are exploited to produce a dual re-entrant/tapered beam etch release process. Released silicon beams are demonstrated over 1200micrometers long and 30micrometers thick with a base width of 300nm.