Study the performance parameters of novel scale FINFET Device in nm Region

Abstract

One of the major challenge with CMOS circuits with 22nm technology & beyond is to buried the issues of increasing in power dissipation of the circuits due to higher order effects & leakage current. The traditional transistor or MOSFET require significant amount of power so the circuit present on the chip will require a large amount of power due to presence of many transistors in the circuit on the chip. CMOS transistors are used for many analog & digital applications. According to Moore's law, the number of transistors in area should double every 18 months. To replace nano scale CMOS, dual gate MOSFET, trigate device called FINFET Used. FINFET permits to lengthening gate scaling beyond the traditional limits sustaining a subthreshold slope, better performance with bias voltage scaling, low loping concertation in the channel. This paper contains the details description of FINFET, its features, its overview, advantages, performance parameters, & prospects of improvements to make it universal for CMOS IC applications towards size, power & speed. This paper presents studies of fundamental physics of Fin Field Effect Transistor, & detail description about the MOSFET structure. This paper presents study Nano scale FINFET with improvement on short channel effect, sources of leakage currents, GIBL, Gate Induced Barrier Lowering, sub-threshold swing is explained.