Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study

Abstract

In each complementary metal-oxide-semiconductor (CMOS) technology generation, design of new device architectures at nanoscale regime becomes quite challenging task due to increased short channel effects (SCEs) and leakage current. A double-gate (DG) MOSFET is an alternative structure. To enhance the performance of DG MOSFET, gate stack (GS) and dual-material gate (DMG) with graded-channel (GC) concepts are amalgamated. Analytical surface potential modeling of GCGS DMDG MOSFET has been done by solving the two-dimensional (2D) Poisson’s equation with suitable boundary conditions. The surface potential profile of GCGS DMDG MOSFET shows a step variation at the interface of two materials. The electrical parameters drain induced barrier lowering (DIBL), sub-threshold swing (SS) and on-current to off-current $\left (\frac {I_{on}}{I_{off}}\right )$ ratio reveals that, DMDG shows a better performance over single-material (SM) DG MOSFET with all (Si3N4, HfO2 and Ta2O5) GS high-k dielectric configurations. An enhanced performance in GCGS DMDG is due to the fact of increased average carrier velocity, reduced drain field effect and leakage current. Further, analog/RF performance parameters such as transconductance (gm), transconductance generation factor (TGF), cut-off frequency (fT), transconductance generation frequency product (TGFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are extracted and compared for both SMDG and DMDG MOSFET with HfO2 GS configuration. The efficacy of analytically modeled results is compared with numerically simulated results obtained from 2D ATLAS device simulator.