Study on CPI behaviors of X Dimension Fan-Out Integration (XDFOI) packages

Abstract

XDFOITM (X Dimension Fan Out Integration) is a package family designed for fan out packages and heterogeneous integration, as XDFOI offers great flexibility to let single die or multi-functional chips, such as logic, memory, power management, RF and passive components, to be packaged by technology evolutions. Based on the approaches of “chip first” and “chip last” processes, XDFOI is designed with the high density I/O and multi-layer metals, polyimide and encapsulation materials like ABF, underfill or molding compound. Various materials applied in the full process flow brings lots of combination of CTE (coefficient of thermal expansion) and meanwhile the CTE mismatch may generate stress on the dielectric materials to influence the performance requirements. It is widely known that manufacturing procedures of heterogeneous integration make the boundaries of foundry backend process of line (BEOL) and bumping process fuzzy. In this paper, three package members in XDFOI family are introduced and the respective process flows are illustrated detailed in order to exhibit the differences between the solutions. Finite-element analysis is integrated along with package building process to predict the stress performances. The simulation results of XDFOI packages divided by packages provide a guideline for estimating maximum stress on the dielectric materials. In order to provide proper guideline to chip packages, data from theoretical calculation are collected, analyzed and merged into design rules for further process optimization and new product introduction. It is considered that the study can greatly improve the overall innovation level and process capabilities.