Study of the Post-Oxidation-Annealing (POA) Process on Deposited High-Temperature Oxide (HTO) Layers as Gate Dielectric in SiC MOSFET

Abstract

In the development of SiC MOSFETs, further improvements are ongoing to improve device performances. One of the critical part at the device level is the gate oxide/semiconductor interface, being the gate oxide a standard SiO2 layer. This work is focused on the investigation of the effect of post oxidation annealing process (POA) carried out after the deposition of high-temperature oxide (HTO) layer used for dielectric gate formation by using NO and N2O gasses. The variation of Dit by applying the POA in N2O is considerable with respect to the as-deposited oxide layer as the density is reduced of about two order of magnitude. A further reduction of interface trap density from 2.3×1010 to 8.5×109 traps/cm2 has been observed when NO POA process was applied. Full vertical power MOSFETs were also analyzed in order to measure the channel mobility of the device. Channel mobility has been seen to raise its value from 45 cm2/Vs to a value of about 62 cm2/Vs when NO-based POA process was performed. NO-based POA process results in a much more effective interface at device level.