Abstract
In this work, a simple Junction-Less Double Gate MOSFET (JL-DGMOS) based Source-Coupled Logic (SCL) inverter circuit is proposed for low power applications in the near and sub-threshold regime. D.C performances like power and delay have been analyzed in depth. JLDG MOSFET have promising advantages over conventional MOSFET to mitigate the short channel effects because of better gate control mechanism. So, the proposed SCL Inverter would be efficacious to offer less power dissipation and less delay. Impact of supply voltage and frequency on the power and delay of the Inverter circuits have been analyzed here. Extensive simulations are done using SILVACO ATLAS to validate the proposed models. Optimization of the process parameters and the supply voltage has been shown to enhance the efficiency.
Published Version
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