Impact Analysis of Dual Material Double Gate Oxide-Stack Junction-Less MOSFET in RFID Memory Cell Realisation

Abstract

In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $\mathrm{I}_\mathrm{ON}/\mathrm{I}_\mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.