Study of Board Level Reliability of eWLB (embedded Wafer Level BGA) for 0.35mm Ball Pitch

Abstract

The number of WLP (Wafer Level Packages) used in semiconductor packaging has experienced significant growth since its introduction due to the small form factor and high performance requirements. With the advancement of fan-out wafer level packaging technology, it is more and more promising compared with fan-in WLP, because it can offer greater feasibility and flexibility for more I/Os, multi-chips, and system integration. But there are some restrictions in possible applications for Fan-In WLP or Fan-out WLP since global chip trends tend toward smaller chip areas with an increasing number of interconnects and better thermal performance. For wider applications of WLP additional development is needed to move past those restrictions. In this study, board level reliability has been performed on eWLB (embedded wafer level BGA) FOWLP (Fanout Wafer Level Package) with 0.35mm ball pitch, with/without UBM, design factors (pad size, pad opening size etc.) with a comprehensive DOE study. The 0.35mm pitch eWLB test vehicles included a 7mm × 7mm package with over 280 balls. A Design of Experiment (DOE) study was reviewed which demonstrates improved Temperature Cycle on Board (TCoB) with thermo-mechanical simulation and experimental results of a daisy chain device. Several DOE test vehicles were prepared with multiple design variables. Daisy chain eWLB test vehicles were used for the TCoB (Temperature Cycle on Board) reliability study in JEDEC test conditions. Additionally, a JEDEC board level drop test was also carried out. With these parametric studies and reliability tests, the final test vehicle passed 1000 cycles TCoB in characteristic life time and also passed 200x drop test. Destructive analyses were performed to investigate potential structural defects and to conduct a failure mode study after reliability test.