Abstract

AbstractThe study of construction of various multi-operand adders is portrayed in this article. The power dissipation and propagation delay of various multi-operand adders are evaluated. Ripple carry adder (RCA) which is designed using binary tree adder (BTA) is evaluated to reveal the probability of delay minimization. That structure and organizational formulation and also the accompanying configuration of RCA and for BTA centered mostly on results of the study. The outcome of both the comparison reveals that the best RCA design has greater performance in terms of delay, area, and energy than for the current RCA design. Adders are simulated using cadence virtuoso software. The gpdk90 nm CMOS technology is used to implement the adder.KeywordsRipple carry adderCarry save adderCarry increment adderCarry-select adderBinary tree adder

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