Abstract
A new device is proposed that utilizes a Si/SiC hetero-junction to potentially overcome one of the major issues holding back the development of SiC MOSFET technology. The proposed device makes use of a thin epitaxial layer of silicon grown on a SiC substrate, on which a high-quality MOS structure can be fabricated. Doped p-type wells in both the silicon and SiC epitaxial layers ensure that the blocking region is contained entirely within the SiC substrate, thus maximising the breakdown voltage of the device. In this study, numerical modelling methods have been applied to a Si/SiC hetero-junction MOSFET structure in order to investigate its feasibility and potential benefits over conventional SiC MOSFETs. Preliminary results on growth of thin silicon layers on SiC – which would be used in fabrication of the real device – are also reported.
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