Study and Analysis of Modified Junction-less SOI MOSFET at 18nm Gate Length

Abstract

The Silicon-on-Insulator junction-less transistors (JLTSOI) were commenced as a competent device for nano-scale applications. The main challenges that can limit the use of junction-less SOI transistors are found out to be the high leakage current, low I on to I off (on-current to off-current) ratio and sub-threshold slope. To compensate this, a new window with slightly doped p-type silicon is opened inside the buried oxide region of a conventional junction-less SOI MOSFET [1]. This paper focuses on optimizing the new windows opened below the channel area, gate length and buried oxide thickness (BOX) thickness of modified junction-less SOI MOSFET, so as to improve the electrical performance at less chip area. In the conventional junction-less transistor this reorganization form a reduction sheet on the interface of the channel area and the new window successfully reduces the amount of leakage current inside the transistor. Considering the diverse spectra of the parameters, the re-enactment of the structures referenced in the examination indicated that the optimized device has superior for the low power digital applications.