Structured glass substrates in wafer- and panel level packaging: Status and recent achievements.

Abstract

Abstract Glasses can be used as core substrate for panel- and/or wafer-level packaging to achieve heterogeneous integration of chiplets and integrated passives in increasingly complex packages. Glass has a large number of advantages: The stiffness of glass (i) allows manufacturing of highly accurate buildup layers. These buildup layers can have manufacturing precision of 1μm and below on large dies with sizes of 50mm x 50mm and more, needed for antenna in package (AiP) applications and high performance computing (HPC). Special glasses can be made with adjusted thermal expansion (CTE) (ii), either adjusted to silicon or with larger thermal expansion to allow packages with buildup layers of epoxy molds and metallization that see high thermal loads either during manufacturing or during operation. Glasses can also be optimized with very good dielectric properties (iii) and can be utilized in antenna-in-package applications. But most of all, economic glass structuring techniques (iv) which can provide millions of vias and thousands of cut-outs in a glass panel are important and are being developed. SCHOTTs Structured Glass Portfolio FLEXINITY® and related technologies provide an excellent starting point for highly sophisticated structured glass substrates required for Advanced Packaging. The biggest hurdle for a large-scale commercialization of glass panel packaging is industrial readiness along the whole process chain. This is needed, to bring glass panel packaging in applications like IC-packaging, RF-MEMS packaging and medical diagnostics or, in combination with cutouts for fan-out, embedding of active and passive components. In addition, metallization processes with good adhesion, excellent electrical properties and high geometric accuracy for glasses are an important step. In the current manuscript, we review the status and discuss our contribution towards achieving industrial readiness for glass in panel- and wafer-level packaging.