Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications

Abstract

Image processing circuits are expected to play an important role in Internet of Things electronic systems. For this type of circuits, errors (e.g., those due to wear out) might not be perceptible to us due to our insensitivity to small variances in images or colors. In the case that errors are acceptable (imperceptible), the systems are very likely to still be functional but with only minor performance degradation. The lifetime of the systems thus can be extended. Although there have been several attributes proposed in the literature to test acceptability of errors, these attributes do not consider human beings’ sensitivity to structural variances of erroneous images. This may result in acceptability misclassification of errors. In this paper, we take this into consideration and propose a new test method to more accurately evaluate acceptability of errors. Compared with the available attributes that can also extract the structural information of images, our method has much lower computation complexity, which is advantageous for shortening test time. This also makes our method hardware efficient. It is shown that the incurred area overhead of our method is low. The proposed method is to be applied periodically in-field to examine the reliability of the target circuit. We thus consider errors that may occur during in-field use. Single/multiple stuck-at faults and noises are considered, and a total of 161 460 erroneous images are generated. The experimental results on these diverse images show that on average the test accuracy of our method is more than 99%.