Error-tolerability enhancement via bit inversion and median filtering for single-bit errors in image processing circuits

Abstract

Error-tolerance has been proposed as a new method to increase effective yield of a system. The basic idea is that faulty chips might be still acceptable as long as their produced errors are insignificant, which is due to the fact that human beings are insensitive to minor variations in sounds, colors and images. It has also been shown that error-tolerance has great applicability to multimedia processing circuits. Based on error-tolerance, if a target chip can have higher error-tolerability, the effective yield (i.e., the fraction of acceptable chips) can become higher. As a result, enhancing error-tolerability of chips is one of the central themes of error-tolerance. This issue, however, has not been addressed in the literature so far. In this work we propose an integrated technique of bit inversion and median filtering to increase the error-tolerability of a chip. We target image processing circuits such as JPEG decoder, and consider faults in the embedded memory in the target circuit. It has been shown that such faults usually induce single-bit errors. Bit inversion is effective to deal with erroneous images when the error rate of a faulty chip is high. The error rate can also thus be reduced. On the other hand, the median filtering is effective to remove errors when the error rate is low. Combining these two methods thus can provide a comprehensive solution. The experimental results for 8000 erroneous images show that by using the proposed technique the error-tolerability can be increased by 52.68 %.