Structural Design of a CMOS Full Low Dropout Voltage Regulator

Abstract

The paper describes structural design of a full (complete) low dropout (LDO) voltage regulator. This LDO is using the following basic subcircuits: bandgap reference (BGR), folded-cascode current operational amplifier (COA), and bias circuit. The regulator is divided in three main blocks, namely, a sub-regulator generating power supply voltage for the BGR, a scaling amplifier providing convenient reference voltage for the LDO, and the LDO itself providing the required output voltage. Each block is consisting of a COA, pass transistor and resistor and represents a dedicated feedback loop. The regulator does not require any on-chip compensation capacitors, and ensures stable operation for a very wide range of capacitive loads. The complete LDO regulator is realized in standard digital 0.13-mum CMOS process for the output voltage of 1.22 V from 1.8-3.3 V power supply.