Structural and Electrical Characterization of Sputter-Deposited Gd0.1Ce0.9O2−δ Thin Buffer Layers at the Y-Stabilized Zirconia Electrolyte Interface for IT-Solid Oxide Cells

Nunzia Coppola,Dario Montinaro,Chiara Sacco,Giovanni Carapella,Pierpaolo Polverino,Alberto Ubaldini,Alice Galdi,Vincenzo Vaiano,Luigi Maritato,Cesare Pianese

doi:10.3390/catal8120571

Abstract

The use of a doped Ceria buffer layer and Physical Vapour Deposition (PVD) techniques for Solid Oxide Fuel Cells (SOFC) fabrication can limit the former, the formation of electrical insulating lanthanum, and strontium zirconates at the cathode/electrolyte interface, whereas the latter allows a better control of the materials interfaces. These effects allow for operation at intermediate temperature ranges. In this work, we study the structural and electrical properties of Gadolinium Doped Ceria (GDC) barrier layer deposited via the room temperature RF Sputtering technique on anode supported electrolytes and then annealed at high temperature. The crystal structure and the surface morphology of the GDC barrier layers have been analyzed and optimized varying the temperature ramp of the post-growth annealing procedure. The electrical behavior of the obtained samples has been investigated by Electrochemical Impedance Spectroscopy and compared to that of standard SOFC with screen-printed GDC barrier layers, the former showing a maximum high frequency and low frequency resistances reduction of about 50% and 46%, respectively, with respect to the latter at an operating temperature of 650 °C. The results clearly show an important improvement of SOFC performances when using sputter deposited GDC layers, linking the electrical properties to the structural and stoichiometric ones.

Highlights

The decreasing of the operating temperature of solid oxide fuel cells (SOFC) down to the so-called intermediate temperature (IT) range (500–700 ◦ C) has recently been shown to allow reduced costs and increased durability [1,2]
X-ray Diffraction (XRD) measurements have been performed on the samples with the sputter-deposited Gadolinium doped Ceria (GDC) layer to check the presence of the right stoichiometry and of the eventual preferential growth direction
35 mm diameter circular SOFC have been fabricated with a GDC barrier layer sputter-deposited at room temperature and annealed at temperatures of 1000 ◦ C using different ramp profiles

Summary

Introduction

The decreasing of the operating temperature of solid oxide fuel cells (SOFC) down to the so-called intermediate temperature (IT) range (500–700 ◦ C) has recently been shown to allow reduced costs and increased durability [1,2]. Several PVD techniques (e.g., oxygen plasma assisted molecular beam epitaxy [7], Pulsed Laser Deposition (PLD) [8,9], and electron beam evaporation [10]) have been investigated in view of their possible use for the GDC buffer layers production process in the industrial fabrication of IT-SOFC. For room temperature sputter-deposited GDC/YSZ crystalline interfaces [14], the possibility to obtain, by a post deposition annealing process, the desired GDC phase with the absence of consistent inter-diffusion phenomena at the GDC/YSZ interface at least for annealing temperatures up to 1000 ◦ C This result is promising in view of the production of SOFC with sputter-deposited GDC barrier layers without any presence of low conducting spurious phases due to the high temperature reaction between GDC and YSZ. GDC layers, allowing to link the structural and stoichiometric quality of the produced samples with the final electrochemical behavior

Morphological and Crystal Structure Characterization

Impedentiometric Characterization

Schematic

Electrochemical Impedance Spectroscopy Measurements

Findings

Conclusions