Strong contact resistance effects on vertical carrier density profile and surface trap density in WSe2 multilayers

Abstract

Conducting channel migration depending on the thickness of 2D multilayers has been demonstrated theoretically and experimentally by ascribing it to the high interlayer barrier and thickness-dependent carrier mobility via an electrostatic gate and drain bias. However, the unique charge carrier transport feature is significantly suppressed when a high contact resistance is exhibited at the metal-to-2D semiconducting multilayers, in addition to the inherent tunneling barrier between neighboring layers. Herein, we report strong channel access contact resistance effects on the vertical carrier density profile and surface trap density along the thickness of WSe2 multilayer transistors. For the constructed top-contact electrodes demonstrating pseudo-ohmic behavior, we observed clear double humps in the second derivative of the transconductance (dgm) curves, implying conducting channel migration along the c-axis of the WSe2 multilayers, regardless of the drain bias (VD) conditions. Meanwhile, at the bottom-contact electrodes, demonstrating a relatively high contact resistance effect, the second hump of dgm exclusively appears at high VD regimes (3.0 V ≤ VD), signaling the restricted channel migration caused by poor contact quality, even in identical WSe2 multilayers. We further confirmed this distinct feature in dgm curves by connecting the top and bottom electrodes to support our observations. Furthermore, low-frequency noise measurements were performed to determine the surface trap density of the supporting dielectrics and the relevant carrier scattering mechanism. Our study provides valuable insight into the effects of contact resistance on carrier transport and the scattering mechanism in WSe2 multilayer transistors, shedding light on the optimization of device performance and contact quality.