Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models

Abstract

With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.