Statistical analysis of low-power SRAM cell structure

Abstract

The reduction of the channel length due to scaling increases the leakage current resulting in a major contribution to the static power dissipation. In this paper, a novel SRAM cell with eight transistors is being proposed to reduce the static hence total power dissipation. When compared to the conventional 6T SRAM and NC-SRAM cell, a significant reduction in the gate leakage current, static and total power dissipation is observed in the proposed SRAM along with higher stability. In the technique employed for the proposed SRAM cell, the operating voltage is reduced in idle mode. The technique led a reduction of 31.2 % in the total power dissipation, a reduction of 40.4 % on static power dissipation, almost without any change in the stability of the cell when compared to the conventional 6T SRAM cell topology. Cadence Virtuoso tools are used for simulation with 90-nm CMOS process technology.