Static divided word matching line for low-power Content Addressable Memory design

Abstract

In this paper, a novel Content Addressable Memory (CAM) word structure with divided word matching line for low-power application is proposed. To reduce the comparison power consumption, the proposed CAM word structure adopts static circuit design to improve the overall system reliability and reduce the power consumption. In addition, a new CAM cell with single bit line circuit design is proposed. The single bit line design requires only one heavy loading bit line, and prevents the frequently switching that designed in conventional basic CAM cell. Based on TSMC 0.25 /spl mu/m CMOS process with 2.5 V supply voltage, a 128 words by 32 bits CAM is designed. The simulation result shows that the power consumption of the proposed CAM is 17.12 mW under 300 MHz operation frequency.