Design of low-power content-addressable memory cell

Abstract

Content addressable memory (CAM), a large amount of energy is generally expended charging and discharging most of the match lines on most cycles. In this paper, a new low-power CAM cell with a single bit line design is proposed to reduce the comparison power of CAM cell. The proposed CAM cell can reduce almost half of heavy capacitance loading and the frequently switching of two complementary bit lines. In the CAM word circuit design, a static pseudo nMOS logic structure with a precomputation approach is used to effectively avoid the frequently switching in the match lines. The CAM design is based on TSMC 0.25 /spl mu/m CMOS process with 2.5 V supply voltage. The power consumption of the proposed CAM is 16.38 mW under 300 MHz operation frequency. Moreover, the power-performance metric is 13.33 fJ/bit/search for random inputs.