Static and dynamic power management in 14nm FDSOI technology

Abstract

This work presents a 14nm technology designed for high speed and energy efficient applications using FDSOI transistors. −34% speed delay at same static power with −100mV V dd supply voltage operation vs 28nm FDSOI is demonstrated. The specific FDSOI features for adjusting the threshold voltage and managing power are highlighted in this paper. It is shown that a light channel doping and reverse back bias are effective to reduce the static leakage and, on the other hand, forward back bias (FBB) can provide dynamic power saving at same speed. All this process & design techniques, in addition to the poly bias capability, makes FDSOI a highly flexible technology to maximize the speed/leakage/power compromise for each application product.