Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS

Abstract

Spin-based devices, in which information is carried via electron spin rather than electron charge, are potential candidates to complement CMOS technology due to the promise of non-volatility and compact implementation of logic gates. One class of such devices is all-spin logic (ASL) which is based on switching ferromagnets by spin transfer torque and conduction of spin-polarized current. Using previously developed physics-based circuit models for ASL, we develop a complete logic family for static ASL comprising of majority logic gates. We compare its performance metrics by means of circuit simulations using our Verilog-A compact models. We also show the novel implementations of sequencing elements (e.g., latch and D flip-flop) to enable clocked ASL. We also refine the models for ferromagnets to include spin relaxation inside ferromagnetic metals (FMs).