A proposal for a magnetostriction-assisted all-spin logic device

Abstract

As scaling CMOS devices is approaching its fundamental limits, a new direction of research has emerged to study beyond-CMOS spintronic devices that use electronic spin as their state variable, offering new and enhanced functionalities. Due to low operating voltage, non-volatility, and efficient implementation of majority gate, a novel spin-based device, all-spin logic (ASL), has been widely studied for applications including interconnects [1], pattern recognition systems [2], and Boolean gates [3]. However, ASL relies on a non-local spin valve (NLSV) structure with the connection to ground being close to the input magnet to ensure non-reciprocity. Thus, a large fraction of injected spins is shunted to ground without ever reaching the output magnet. In addition, supply clocking is envisioned to reduce energy dissipation [3]. Even then, a 32-bit addition by ASL compared to that by CMOS, requires 5 orders of magnitude more energy. In this paper, we propose a novel device that uses voltage-controlled strain-mediated magnetization switching [4] and spin transfer torque (STT) to perform the first and second 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> of switching, respectively. The STT is created in a conventional spin valve instead of the NLSV structure used in ASL. Hence, the wasteful shunt path to ground is eliminated. Non-reciprocity is ensured through a clocking scheme in which the input and output magnets are oriented along the stable easy axis and the meta-stable saddle point of energy profile, respectively. It has been shown that the deterministic switching of a magnet from a saddle point is more efficient in terms of delay and energy and affected less by thermal noise [5], [6]. The device can be cascaded in a domino logic scheme, Fig. 1 a, by performing the first 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> switching for all cascaded logic gates simultaneously; therefore, the overall delay of a more complicated circuit like a 32-bit adder significantly improves.