SPICE models for metallic all-spin-logic devices and interconnects

Abstract

As Si CMOS technology approaches its scaling limits, there is a global search for novel devices based on state variables other than electronic charge. Among the potential alternative state variables, electron spin has received special attention thanks to its advantages in terms of robustness, non-volatility, and enhanced functionality. Recently, Purdue researchers proposed an all-spin logic (ASL) device that is a derivative of the nonlocal spin-valve structure and accomplishes the five essential characteristics for logic devices: concatenability, nonlinearity, feedback elimination, gain, and a complete set of Boolean operations [1], [2]. Various materials such as metals (copper and aluminum), semiconductors (silicon and gallium arsenide), and even novel carbon-based material such as graphene may be used to implement the channel in an ASL device. Metals are particularly attractive because of their high conductivity, which helps to reduce the “conductivity mismatch” problem [3] prevalent in spin devices with both semiconducting and graphene channels. In this talk, compact models are presented for the spin transport parameters in Cu and Al wires that capture the impact of size effects including surface scattering and grain boundary scattering at nanoscale dimensions [4]. The proposed models have been calibrated with experimental data from mesoscopic lateral spin valves. To model an ASL interconnect, one needs to account for the magnet dynamic, electronic and spintronic transport through magnet to non-magnet interfaces, electric currents, and spin diffusion. A comprehensive set of SPICE models that captures all these effects are described [5]. Finally, the models are used to predict the delay and energy dissipation of ASL devices and interconnects as functions of channel length and cross-sectional dimensions