Abstract
Logic locking is a promising design-for-trust solution to the hardware IP piracy problem. Early logic locking methods for combinational circuits were susceptible to Boolean satisfiability (SAT) based attacks. Recently proposed SAT-based attack methods have shown success in unlocking locked sequential logic circuits without scan chain access. This paper introduces a new logic locking scheme that locks a sequential circuit on the occurrence of a chosen rare state transition. A novel approach to selecting suitable states for the ‘locking’ transition using the gate-level netlist of the design is proposed. Two unique methods to estimate the rarity of occurrence of the chosen states are discussed. Additionally, techniques to increase the error rate of the locked design are presented. The attack resiliency of the proposed technique against the Sequential SAT attack is demonstrated using several standard benchmark circuits.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call