On SAT-Based Attacks On Encrypted Sequential Logic Circuits

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Logic encryption has emerged as a solution to the hardware intellectual property (IP) protection prob-lem. In recent years, many attack methods have been proposed to counter the protection offered by logic encryption. Most state-of-the-art logic encryption schemes have been shown to be susceptible to one or more of these attack methods. Furthermore, defense methods on sequential circuits assume that a Boolean satisfiability (SAT) based attack can be applied to a sequential circuit only in the presence of a design-for-testability (DFT) architecture. In this paper, we examine the effectiveness of applying the SAT-based attack on logic encrypted sequential circuits lacking a scan architecture. We evaluate the effect of the presence of flip-flop chains in the circuit on the sequential SAT attack time. Furthermore, we analyze the evaluation results and propose an enhancement to the sequential SAT attack.