Abstract

Nonvolatile and cascadable stateful logic operations are experimentally demonstrated within a 1 k-bit one-transistor-one-resistor (1T1R) resistive random access memory (RRAM) array, where NAND gates serve as the building blocks. A robust dual-gate-voltage operation scheme is proposed. The effects of the transistor ON logic operation and the robustness to device parameter variations are discussed. The parallel 4-bit bitwise XOR operation is experimentally implemented in the 1T1R array by cascading NAND gates. This letter presents a feasible approach to in-memory computing for large-scale circuits.

Highlights

  • C ONVENTIONAL von Neumann architecture with separated processing and memory unit is facing the bottleneck of computation speed and energy efficiency as applications become more data-centric [1]

  • We experimentally demonstrate the stateful logic operation in a 1k-bit 1T1R resistive random access memory (RRAM) array, where the NAND gates serve as the building blocks

  • Stateful logic operations are successfully demonstrated in the fabricated 1k-bit 1T1R RRAM array

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Summary

INTRODUCTION

C ONVENTIONAL von Neumann architecture with separated processing and memory unit is facing the bottleneck of computation speed and energy efficiency as applications become more data-centric [1]. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. R-V logic [11], [12] is performed by reading the resistance of input cells and comparing it with a threshold to determine the output voltage. In R-R logic [14]–[22], the input and output are both resistance of the non-volatile memory elements Such R-R logic is a truly nonvolatile and cascadable in-memory Boolean operation, which is referred to as stateful logic [2]. We experimentally demonstrate the stateful logic operation in a 1k-bit 1T1R RRAM array, where the NAND gates serve as the building blocks. A dual-gate-voltage operation scheme is proposed for stateful logic operations in 1T1R array. Electrical measurements were carried out using STM32F103 Series MCUs, Agilent B1500A semiconductor parameter analyzer, Agilent 81160A pulse function generator, and Agilent Infiniium MSO9404A Series Oscilloscopes

STATEFUL LOGIC OPERATIONS
CONCLUSION
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