Staggered Pixel Layout to Reduce Area and Increase Full Well Capacity in CMOS Image Sensors

Abstract

CMOS image sensor’s ability to collect light depends, amongst others, on its full well capacity (FWC) which is the capability of a pixel of storing electrons. The FWC can be improved either by expensive and time-consuming process modifications or by increasing the pixel photodiode area. Optimizing the pixel layout is crucial to increase the photodiode area at a given pixel pitch. In this article, we present a novel layout technique that reduces the area occupied by the in-pixel transistors by reorganizing the shared diffusions. Such optimization is demonstrated to increase the area of the photodiode for a given pixel pitch and, hence, the fill factor (FF). Both a mathematical model of the methodology and experimental results of pixels manufactured in a commercially available technology are presented. We prove that the technique is particularly effective for small pixel pitches and can lead to an increase in FF and FWC of at least 20% in a 4-transistor CMOS pixel with 2.4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pitch.