A 64Mpixel CMOS Image Sensor with 0.56μm Unit Pixels Separated by Front Deep-Trench Isolation

Abstract

CMOS image sensors (CISs) with deep-submicron pixels are now in high demand, as high-end mobile devices are equipped with multiple camera modules that are used for ultra-high-resolution imaging [1], [2]. The biggest challenges with small pixels are to maintain dynamic range (DR), signal-to-noise ratio (SNR), and sensitivity compatible with a sensor with larger pixels. A back-illuminated stacked sensor with front deep-trench isolation (FDTI) and shallow-trench isolation (STI) for inter-pixel and inter-node isolation respectively appears promising for continuous pixel-size reduction in terms of maximizing DR with large full-well capacity (FWC) while minimizing optical/electrical crosstalk [3]–[5]. However, dark current may increase by strong electric fields (e-field) near defective FDTI interfaces if more doping is applied to a small photodiode (PD) to increase FWC. In addition, the FDTI/STI structure limits the area of in-pixel transistor amplifiers, and it may deteriorate dark temporal noise (TN) as pixel pitch becomes smaller. Furthermore, optical crosstalk between different color filters (CFs) is more problematic as pixel size enters the sub-wavelength scale. In this work, a back-illuminated 64Mpixel CIS with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.56\mu\mathrm{m}$</tex> -pitched pixels is reported. We present pixel designs and fabrication processes that achieve competitive FWC, dark current, TN, and optical performances with small pixels.