Analysis of Transfer Gate Doping Profile Influence on Dark Current and FWC in CMOS Image Sensors

Jiangtao Xu,Quanmin Chen,Zhiyuan Gao

doi:10.1109/jeds.2020.3036841

Jiangtao Xu, Quanmin Chen + Show 1 more

Open Access

https://doi.org/10.1109/jeds.2020.3036841

Copy DOI

Abstract

The influence of transfer gate (TG) doping profile on dark current and full well capacity (FWC) has been investigated in this article. By analyzing the non-uniform doped TG channel in 4T pixel, a potential profile with a barrier is extracted at TG off state. In this analysis, twice P-type doping under TG directly determine the barrier position and its height. By adjusting the two P-type doping length under TG, dark current under TG is drained to floating diffusion instead of pinned photodiode, which is divided by the barrier. On the other hand, the increase of doping implantation under TG is beneficial to FWC due to the increased barrier height. Technology computer aided design (TCAD) simulations are performed to verify the analysis. Furthermore, a test chip with 6 μm × 6 μm pixels fabricated in a 0.11 μm CMOS process is tested. In our design, by shortening LTG_PD and extending LTG_FD, dark current reduces by 15% and 17%, respectively. In the case of a certain doping profile under TG, shorting the length of TG from 0.6 μm to 0.4 μm helps reduce dark current by 30% at the cost of 6% FWC reduction.

Highlights

In recent years, CMOS image sensors (CISs) have developed rapidly, benefiting from its low power consumption, miniaturization, and compatibility with standard CMOS processes [1]
MEASUREMENT RESULTS Dark current and full well capacity (FWC) measurement is performed on a CIS chip constituted of a set of 6 μm pitch 4T-pinned photodiode (PPD) pixels
The second is composed by pixels with different transfer gate (TG) lengths

Summary

Introduction

CMOS image sensors (CISs) have developed rapidly, benefiting from its low power consumption, miniaturization, and compatibility with standard CMOS processes [1]. The implantations of PPD and TG must be carefully optimized in order to achieve the high charge transfer efficiency, low dark current, and large full well capacity (FWC) [2]–[4]. A small variation on the transfer gate design and technology will impact the performance dramatically. Negative bias at the TG is proposed to reduce the generation current under TG [6]–[8]. When the TG is biased at a negative voltage, the TG channel is in the state of accumulation. Marcelot et al has demonstrated that a dark current reduction is achieved when TG is at positive bias voltage in off state [10]. The purpose of this article is to analyze the effect of the TG

Objectives

Results

Discussion

Conclusion