Abstract
Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.
Highlights
Conventional pixel design for complementary metal–oxide–semiconductor (CMOS) image sensors (CIS) commonly uses fully depleted photodiodes as a photo-sensing element
Developments, the photodiode structure evolved from the early planar pinned photodiode (PPD) [1,2]
As charges are stored in deep PPD, it becomes more difficult to drain them via a surface transfer gate (TG) for the reading
Summary
Conventional pixel design for complementary metal–oxide–semiconductor (CMOS) image sensors (CIS) commonly uses fully depleted photodiodes as a photo-sensing element. The proposed pixel quantity of charges to establish, by field effect, a sufficient density of oppositely charged carriers at structure takes benefit from capacitive deep trench isolation (CDTI), formerly developed for dark current the silicon (backside) surface. It plays the role of a photon transmission layer through its optical reduction [11] and more recently for fully depleted memories for global shutter applications [7,12].
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