Spin-Based Imprecise 4-2 Compressor for Energy-Efficient Multipliers

Abstract

The 4-2 compressor has been widely employed in the design of multipliers. The considerable impact of 4-2 compressors on the efficiency of multipliers has created significant research interests in design of new compressor structures. In the vast range of error resilient applications, multiplication plays an important role in performing computation. Imprecise (approximate) realization of multiplication results in considerable area, power and delay efficiency at the cost of negligible computational errors. In this paper, an imprecise 4-2 compressor is presented. Spintronic devices as promising alternative technologies for silicon-based FET are considered for implementation of the proposed design. All designs are simulated exhaustively at the circuit level and application level. The conducted simulations indicate the superiority of the proposed design compared with the related state-of-the-art in all aspects. The proposed design has more than two and three times lower power and power delay product, respectively, compared to the best previous design.