SPICEless RTL design optimization of nanoelectronic digital integrated circuits

Abstract

The previous chapter discussed various steps of high-level synthesis (HLS) which are used for design exploration of digital integrated circuits. It then discussed specific methods for dynamic power dissipation optimization as well as synthesis of hardware-trojan free digital integrated circuits. The methods relied on various bio-inspired algorithms for design space exploration. As complementary material of the previous chapter, this chapter presents HLS methods for leakage-optimal digital integrated circuit design exploration. Specifically, a paradigm shift approach is presented in which the complete HLS flow is performed without use of any electronic design automation (EDA) tool. All the associated tasks such as modeling, characterization, and optimization are performed using non-EDA tools, and hence this is called the “SPICEless” approach. For a specific objective of nanoelectronic digital integrated circuits, gate-leakage power dissipation is targeted.