Integrated RF transformer and power combiner design in 150nm CMOS process

Abstract

An integrated passive power combiner is discussed and characterized based on test structure fabricated in a 150nm LFoundry CMOS process. The power combiner uses differentially driven coupled transformers as a basic building block. We discuss first the constraint driven sythesis of the transformer itself and the device modeling with a rapid RLCk model extractor. Helic's electronic design automation (EDA) tools are used for both, synthesis and extraction of the passive devices. The accuracy of the extracted transformer model is proven by comparison to an EM tool. The fabricated power combiner structure is finally extracted with the same EDA toolset and compared to measured data from on-wafer experiments. Good agreement is achieved in all cases proving the accuracy of the proposed synthesis and extraction methodology for complex RF IC designs. I. INTRODUCTION Passive device modeling in advanced semiconductor pro- cesses is a constantly growing request by integrated circuit (IC) designers, especially in the domain of mixed-signal and RF design. Electronic design automation (EDA) tools are expected to provide accurate and reliable models to IC designers seeking to achieve first pass silicon. Furthermore, rapid extraction and simulation times are crucial parameters for achieving optimum designs and shorter time to market cycles. Planar 2.5D or full wave 3D EM solver solutions based on Finite-Difference (FD), Finite-Elements (FE), and Method of Moments (MoM) are used for simulation and extraction of passive devices. The electromagnetics behind these methods are well established and yield the needed accuracy, but long extraction times con- strain the device type they can handle. Depending on the device layout and EM solver meshing specifications large simulation times may result. Scope of this work is to present a rapid device synthesis and extraction methodology which is capable of dealing with generic interconnects as well as any type of passive device supported by today's silicon technologies. Helic's VeloceRaptor modeling engine is seamlessly integrated in the IC design flow (1) and allows for sythesis of custom devices and rapid RLCk model extraction for passives such as inductors, transformers, and interconnects. Helic's toolset allows for synthesis and extraction of custom passive devices by creating lumped element models which are translated into a SPICE type netlist. In the following sections a design of an integrated passive combiner structure is presented based on coupled transformer devices. The constraint driven transformer design is described in Section II. In Section III a transformer device is used for the extraction of an equivalent passive model with VeloceRaptor. Finally, in Section IV the proposed power combiner topology is discussed and its simulated performance is compared against on-wafer silicon measurements. II. CONSTRAINT DRIVEN TRANSFORMER DESIGN Designing complex passive devices such as integrated transformers in not an easy task even for an experienced IC designer. Numerous and often competing design and optimiza- tion parameters have to be considered, such as device size, losses, matching conditions and transformation ratio. Helic's EDA tools allow for a constraint driven transformer design in order to meet the desired design goals across a variety of parameters. Assuming a differentially driven transformer, we begin with the circuit topology shown in Fig. 1. P 1 P 2